Method of manufacturing flash memory device

ABSTRACT

A method of manufacturing a flash memory device includes the steps of forming trenches by forming a tunnel oxide layer and a conductive layer for a floating gate over a semiconductor substrate, and then etching a portion of the conductive layer, the tunnel oxide layer and the semiconductor substrate to form the trenches, filling the trenches with an insulating layer to form isolation layers projecting above the floating gate, forming spacers on sidewalls of the isolation layers projecting above the floating gate, etching the conductive layer using the spacers as a mask, thereby forming a U-shaped conductive layer, removing the spacers, etching the top surface of the isolation layers, thereby controlling an Effective Field Height (EFH) of the isolation layer, and forming a dielectric layer and a conductive layer for a control gate on the resulting surface.

CROSS-REFERENCE TO RELATED APPLICATION

Priority to Korean patent application number 2006-59522, filed on Jun.29, 2006, the disclosure of which is incorporated by reference in itsentirety, is claimed.

BACKGROUND OF THE INVENTION

The invention relates, in general, to flash memory devices and, moreparticularly, to a method of manufacturing a flash memory device inwhich interference between floating gates can be reduced and thecoupling ratio can be increased.

In a NAND flash memory device, a plurality of cells for storing data areconnected in series to form one string. A drain select transistor and asource select transistor are formed between the cell string and thedrain and between the cell string and the source, respectively. In thecell of the NAND flash memory device, a gate in which a tunnel oxidelayer, a floating gate, a dielectric layer and a control gate arestacked is formed at a specific region on a semiconductor substrate.Junctions are formed at both sides of the gate.

In the NAND flash memory device constructed above, the state of the cellis influenced by the operation of neighboring cells. It is thereforevery important to maintain a constant cell state. A phenomenon in whichthe state of the cell is changed due to the operation of neighboringcells (i.e., a program operation) is called an interference phenomenon.In other words, if a second cell adjacent to a first cell to be read isprogrammed, a threshold voltage higher than that of the first cell isread due to a capacitance phenomenon caused by a change in the chargesof the floating gate of the second cell. Therefore, although the chargeof the floating gate of the first cell is not changed, the actual stateof the first cell appears distorted due to a change in the state ofneighboring cells. The state of the cell is changed due to theinterference phenomenon, resulting in a degraded yield of the failureratio. Accordingly, it is desirable to maintain a constant cell state byminimizing the interference phenomenon.

Meanwhile, in a manufacturing process of a general NAND flash memorydevice, part of the isolation layer and the floating gate is formedusing a Self-Aligned Shallow Trench Isolation (SA-STI) process. Theprocess is described below with reference to FIG. 1.

A tunnel oxide layer 11 and a first polysilicon layer 12 are formed overa semiconductor substrate 10. Specific regions of the first polysiliconlayer 12 and the tunnel oxide layer 11 are etched. The semiconductorsubstrate 10 is etched to a specific depth, forming trenches. Thetrenches are filled with an insulating layer. A polish process is thenperformed to form isolation layers 13 in the trenches. Thereafter, asecond polysilicon layer 14 is formed and then etched to form floatinggates 12 and 14. A dielectric layer 15 and a third polysilicon layer 16for a control gate are formed over the floating gates 12 and 14.

If the flash memory device is fabricated by the SA-STI process describedabove, interference may occur between the first polysilicon layers 12because the isolation layers 13 are formed between neighboring firstpolysilicon layers 12 serving as the floating gates.

FIG. 2 is a graph illustrating the floating gate interference couplingratio as a function of floating gate height and the gate-to-gatedistance between floating gates of a flash memory device.

Referring to FIG. 2, inter-gate interference is inversely proportionalto the distance between the floating gates and proportional to theheight of the floating gate. In other words, if the distance between thefloating gates increases and the height of the floating gate decreases,interference is reduced. However, if the height of the floating gatedecreases, the interface area of the floating gate and the control gateis reduced and the coupling ratio is reduced.

SUMMARY OF THE INVENTION

Accordingly, the invention addresses the above problems and provides amanufacturing method for a flash memory device. In the method, afloating gate is partially etched to have a U-shaped form so that theinterfacial area between the floating gate and a control gate can beincreased and the coupling ratio can be increased accordingly. A portionof an isolation layer between the floating gates is etched so that thecontrol gate to be formed subsequently is disposed between the floatinggates, thereby reducing the interference phenomenon.

According to an aspect of the invention, a method of manufacturing aflash memory device includes the steps of forming trenches by forming atunnel oxide layer and a conductive layer for a floating gate over asemiconductor substrate, and then etching a portion of the conductivelayer, the tunnel oxide layer and the semiconductor substrate to formthe trenches, filling the trenches with an insulating layer to formisolation layers projecting above the floating gate, forming spacerssidewalls of the isolation layers projecting above the floating gate,etching the conductive layer using the spacers as a mask, therebyforming a U-shaped conductive layer, removing the spacers, etching thetop surface of the isolation layers, thereby controlling an EffectiveField Height (EFH) of the isolation layer, and forming a dielectriclayer and a second conductive layer for a control gate on the resultingsurface.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view illustrating a conventional method ofmanufacturing a flash memory device;

FIG. 2 is a graph illustrating the floating gate interference couplingratio as a function of floating gate height and distance betweenfloating gates of a flash memory device; and

FIGS. 3 to 8 are cross-sectional views illustrating a method ofmanufacturing a flash memory device according to an embodiment of theinvention.

DESCRIPTION OF SPECIFIC EMBODIMENTS

Now, a specific embodiment of the disclosure is described with referenceto the accompanying drawings.

FIGS. 3 to 8 are cross-sectional views illustrating a method ofmanufacturing a flash memory device according to an embodiment of theinvention.

Referring to FIG. 3, a wall formation ion implant process and an ionimplant process for controlling the threshold voltage are performed on asemiconductor substrate 100. A tunnel oxide layer 101, a conductivelayer 102 for a floating gate, a buffer oxide layer 103, a nitride layer104 for a hard mask are sequentially formed over the semiconductorsubstrate 100. The conductive layer 102 can be formed of a polysiliconlayer. The buffer oxide layer 103 protects the conductive layer 102 whenremoving the nitride layer 104. Thereafter, the buffer oxide layer 103,the conductive layer 102, and the tunnel oxide layer 101 are selectivelyetched by using an etch process using the nitride layer 104 as a mask.The semiconductor substrate 100 is etched to form trenches 105.

An insulating layer, such as a high density plasma (HDP) oxide layer, isformed on the entire surface so that the trenches 105 are filled. Apolishing process, such as a chemical-mechanical polish (CMP), isperformed on the insulating layer such that the nitride layer 104 isexposed, thereby forming isolation layers 106 within the trenches 105.

Referring to FIG. 4, an etch process is performed to remove the nitridelayer 104. Thereafter, an oxide layer 107 is formed above the entireresulting structure of the semiconductor substrate 100 including theisolation layer 106 and the conductive layer 102. The oxide layer 107 ispreferably formed to a thickness of 50 Angstrom to 100 Angstrom.

Referring to FIG. 5, an etch process is performed to form spacers 108including a portion of the oxide layer 107 and a portion of the bufferoxide layer 103 remaining only on the side walls of the exposedisolation layer 106.

Referring to FIG. 6, the top surface of the conductive layer 102 isetched by an etch process using the spacers 108 as etch masks, so thatthe conductive layer 102 has a

shape, that is, a U shape. The etch process is preferably performed byusing HBr/O₂, HBr/Cl₂/O₂ or Cl₂/O₂ having a high selectivity withrespect to an oxide layer. Further, the thickness of the bottom of theconductive layer 102, (i.e. the distance from the tunnel oxide layer 101to the bottom of the U-shaped gap defined by the etched conductive layer102) preferably ranges from 300 Angstroms to 500 Angstroms. Furthermore,an angle α formed by an inner sidewall and the bottom of the etchedconductive layer 102 is preferably in the range of 91 to 95 degrees.

Referring to FIG. 7, an etch process is performed to remove the spacers108. An oxide layer recess process is then performed in order to loweran Effective Field Height (EFH) of the isolation layer 106, which can bean oxide layer (e.g., an HDP oxide layer). The EFH is preferably withina range of 200 to Angstroms 400 Angstroms.

Referring to FIG. 8, a dielectric layer 109 is formed on the entirestructure of the semiconductor substrate 100, including the conductivelayer 102 having the U shape. The dielectric layer 109 preferably has anoxide-nitride-oxide (ONO) structure in which a first oxide layer, anitride layer and a second oxide layer are sequentially formed.

A conductive layer 110 for a control gate is formed on the dielectriclayer 109. The conductive layer 110 is preferably formed of apolysilicon layer. The dielectric layer 109 and the conductive layer 110completely fill the U-shaped gap between opposing sidewalls of theetched conductive layers 102, so that the opposing sidewalls of theconductive layers 102 are isolated from each other. Accordingly, theinterference phenomenon between adjacent conductive layers 102 can beimproved.

As described above, according to the invention, a floating gate ispartially etched to have a U shape. Accordingly, the interfacial area ofthe floating gate and a control gate can be increased, the couplingratio can be increased, and the program speed of a cell can be improved.

Furthermore, an isolation layer between the floating gates is partiallyetched so that a control gate to be formed subsequently is disposedbetween the floating gates. It is therefore possible to reduce theinterference phenomenon.

Although the foregoing description has been made with reference to theillustrated embodiments, it is to be understood that changes andmodifications may be made by the ordinarily skilled in the art withoutdeparting from the spirit and scope of the disclosure and appendedclaims.

1. A method of manufacturing a flash memory device, comprising the stepsof: forming a tunnel oxide layer and a conductive layer for a floatinggate over a semiconductor substrate; etching a portion of the conductivelayer, the tunnel oxide layer, and the semiconductor substrate to formtrenches; forming isolation layers at the trenches, wherein theisolation layers project above floating gate; forming spacers on exposedsidewalls of the isolation layers projecting above the conductive layer;etching the conductive layer using the spacers as an etch mask, therebyforming a U-shaped conductive layer; removing the spacers; etching thetop surface of the isolation layers, thereby controlling an EffectiveField Height (EFH) of the isolation layer; and forming a dielectriclayer and a second conductive layer for a control gate on the resultingsurface.
 2. The method of claim 1, further comprising, before the stepof forming the trenches, performing a wall formation ion implant processand an ion implant process for controlling threshold voltage on thesemiconductor substrate.
 3. The method of claim 1, wherein the step offorming the trenches comprises the steps of: sequentially forming thetunnel oxide layer, the conductive layer for the floating gate, a bufferoxide layer, and a nitride layer over the semiconductor substrate;performing an etch process employing a mask to pattern the nitridelayer; thereby forming a hard mask; performing an etch process using thehard mask, sequentially etching the buffer oxide layer, the conductivelayer for the floating gate, and the tunnel oxide layer, therebyexposing a specific region of the semiconductor substrate; and etchingthe specific region of the exposed semiconductor substrate to form thetrenches.
 4. The method of claim 1, wherein the conductive layer for thefloating gate and the second conductive layer for the control gate eachcomprise a polysilicon layer.
 5. The method of claim 1, wherein the stepof forming the spacers comprises the steps of: forming an oxide layerabove the resulting structure of the semiconductor substrate includingthe isolation layers and the conductive layer for the floating gate; andperforming an etch process to form the spacers such that the oxide layerremains only on sidewalls of the isolation layers projecting above thefloating gate.
 6. The method of claim 5, wherein the oxide layer has athickness of 50 Angstroms to 100 Angstroms.
 7. The method of claim 1,wherein the U-shaped conductive layer comprises a bottom portion havinga thickness in a range of 300 Angstroms to 500 Angstroms.
 8. The methodof claim 1, wherein the step of etching the conductive layer comprisesusing an etch gas selected from the group consisting of HBr/O₂,HBr/Cl₂/O₂, and Cl₂/O₂, wherein the etch gas has a high etch selectivityrelative to an oxide.
 9. The method of claim 1, wherein the U-shapedconductive layer comprises a bottom portion and a sidewall, the anglebetween the bottom portion and the sidewall being in a range of 91degrees to 95 degrees.
 10. The method of claim 1, wherein the step ofetching the top surface of the isolation layers to control the EFHcomprises performing an oxide layer recess process so that the resultingEFH of the isolation layer is in the range of 200 Angstroms to 400Angstroms.